PLL602-35/-37/-38/-39

750kHz – 800MHz Low Phase Noise Multiplier XO

Universal Low Phase Noise IC’s

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4

3. General Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Fout<24MHz

25/25/15

24MHz<Fout<96MHz

65/45/30

Supply Current,

Dynamic (with

Loaded Outputs)

PECL/LVDS/CMOS

96MHz<Fout<800MHz

100/80/40

mA

Operating Voltage

2.97

3.63

V

Output Clock

Duty Cycle

@ 1.25V (LVDS)

@

45

45

45

50

50

50

55

55

55

%

Short Circuit

Current

±50

mA

4. Jitter Specifications

PARAMETERS

CONDITIONS

FREQUENCY

MIN.

TYP.

MAX.

UNITS

19.44MHz

2.2

77.76MHz

3.5

155.52MHz

4.3

With capacitive decoupling be-

tween VDD and GND.

Over 10,000 cycles.

622.08MHz

5.0

ps

19.44MHz

17

77.76MHz

25

155.52MHz

27

Period jitter Peak-to-

With capacitive decoupling be-

tween VDD and GND.

Over 10,000 cycles.

622.08MHz

35

ps

155.52MHz

2.6

4

Integrated 12 kHz to 20 MHz

622.08MHz

2.5

4

ps

5. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

19.44MHz

-80

-108

-132

-142

-150

77.76MHz

-72

-103

-122

-130

-125

155.52MHz

-65

-95

-120

-125

-121

to carrier

(typical)

622.08MHz

-55

-85

-109

-115

-110

dBc/Hz

6. CMOS Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

10

mA

Output drive current

10

mA

Output Clock Rise/Fall Time

0.3V ~ 3.0V with 15 pF load

2.4

ns