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ECE1200 数据表(PDF) 72 Page - Microchip Technology |
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ECE1200 数据表(HTML) 72 Page - Microchip Technology |
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72 / 87 page ![]() ECE1200 DS00003093C Draft-page 72 2018-2021 Microchip Technology Inc. 9.7.2 G3 TO S0 VIRTUAL WIRE DETAIL AS PRIMARY ESPI SLAVE FIGURE 9-2: G3 TO S0 VWIRES, PRIMARY SLAVE 1.8V eSPI_RESET# BOOT_DONE input pin 3.3V 1.8V eSPI_CS0# on eSPI_CS# eSPI Traffic Running S0 Main Power Good S0 BIOS SW LPC_EN input pin 3.3V 3.3V PLTRST# input pin S5 system PCH_PWROK y (Delayed) (Strapped) Power State Changes (Ignored) S0 CPU HW I/O Traffic Internal: BAR Setup, Clock Setup, SERIRQ and LPC Setup Bridged Traffic Booting from S5 G3 or DSW to S5 Constant throughout, in their initial states: OOB_RST_WARN = 0 OOB_RST_ACK = 0 HOST_RST_WARN = 0 HOST_RST_ACK = 0 ERROR_FATAL = 0 ERROR_NONFATAL = 0 DNX_WARN = 0 DNX_ACK = 0 SUS_PWRDN_ACK = 0 HOST_C10 = 0 |
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