Preliminary

PLL600-27/-37

Ultra Low Current XO 10 MHz to 52 MHz

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com Rev 08/12/04 Page 1

FEATURES

• Low phase noise (-130 dBc @ 10kHz offset).

• CMOS output with OE tri-state control.

• Selectable oscillator “on” or “off” ( Sleep Mode )

feature in output disable mode

• Ultra Low current consumption ( <2mA, <1.5mA

at 27MHz, 3.3V respectively for PLL600-27 and

PLL600-37)

•

Ultra Low disable mode current (<2uA when

disabled with osc. off)

• 12mA drive capability at TTL output.

• Low jitter (RMS): 2.5ps period jitter.

• 1.8V, 2.5V and 3.3V DC operation.

• Available in 8 pin SOIC, 6 pin SOT or DIE.

DESCRIPTION

The PLL600-27/-37 form a low cost family of XO

IC’s, designed to consume the lowest current on the

market for the 10MHz to 52MHz range. It accepts

fundamental resonant mode crystal input from 10 to

52MHz. Providing less than -130dBc at 10kHz offset

at 30MHz and with a very low jitter (2.5 ps RMS pe-

riod jitter) makes this chip ideal for applications re-

quiring low current frequency sources.

BLOCK DIAGRAM

PIN ASSIGNMENT (PACKAGE)

8 pin SOIC

6 pin SOT

SELECTION TABLE

OE^

OSCSEL^*

OUTPUT

0

0

Disabled - osc. off

0

1

Disabled - osc. on

1

0

Enabled

1

1

Enabled

^ Internal Pull-up, default value is ‘1’ when not connected.

* Not available in 6 pin SOT package.

XTAL

OSC

XIN/FIN

XOUT

CLK

OE

OSCSEL

1

2

3

4

XIN/FIN

5

6

7

8

N/C

GND

OSCSEL^

XOUT

OE^

VDD

CLK

^ : denotes internal pull-up

1

2

3

4

5

6

CLK

GND

XIN/FIN

VDD

XOUT

OE^

^: denotes internal Pull-up