PLL520-38/-39

PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

XIN

2

I

Crystal input. See Crystal Specifications on page 2.

XOUT

3

I

Crystal output. See Crystal Specifications on page 2.

OE

6

I

Output enable. See Output Enable Logic table on page 1.

VCON

7

I

Voltage control input.

GND

8, 14

P

Ground.

CLKT

11

O

True output PECL (PLL520-38) or LVDS (PLL520-39).

CLKC

13

O

Complementary output PECL (PLL520-38) or LVDS (PLL520-39).

N/C

4,5,9,10,15,16

-

Not connected.

VDD

1, 12

P

Power supply.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

4.6

V

Input Voltage, dc

-0.5

V

Output Voltage, dc

-0.5

V

Storage Temperature

-65

150

°C

Ambient Operating Temperature*

-40

85

°C

Junction Temperature

125

°C

Lead Temperature (soldering, 10s)

260

°C

ESD Protection, Human Body Model

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other

conditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

2. Crystal Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

CX+

2

Built-in Capacitance

CX-

2

Inter-electrode capacitance

65MHz to 130MHz

(VDD=3.3V)

2.6

pF

C0/C1 ratio (gamma)

γ

300

-

Oscillation Frequency

OF

Fund.

65

130

MHz