Preliminary

PLL600-27B

Ultra Low Current XO 10 MHz to 52 MHz

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/03/05 Page 3

2. AC Electrical Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Crystal Frequency

10

52

MHz

At power-up

(Vdd reaches 1.62V)

10

ms

Disable to enable, osc. Off

10

ms

Settling time

Disable to enable, osc. On

500

µs

0.8V ~ 2.0V with 10 pF load

1.15

Output Clock Rise/Fall Time

0.3V ~ 3.0V with 15 pF load

2.4

ns

VDD sensitivity

Frequency vs. VDD +/- 10%

0.8

0.8

ppm

Output Clock Duty Cycle

45

50

55

%

3. Jitter and Phase Noise Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

RMS Period Jitter

(1 sigma – 10,000 samples)

With capacitive decoupling

between VDD and GND.

2.1

2.5

ps

Phase Noise relative to carrier

27MHz @100Hz offset

-108

dBc/Hz

Phase Noise relative to carrier

27MHz @1kHz offset

-135

dBc/Hz

Phase Noise relative to carrier

27MHz @10kHz offset

-147

dBc/Hz

Phase Noise relative to carrier

27MHz @100kHz offset

-148

dBc/Hz

Phase Noise relative to carrier

27MHz @1MHz offset

-148

dBc/Hz

4. DC Specification

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

At 10MHz, Cload=15pF

1.3

1.5

At 13.5MHz, Cload=15pF

1.5

1.7

At 17.7MHz, Cload=15pF

1.7

2.0

At 27MHz, Cload=15pF

2.3

2.7

Supply Current, Dynamic,

with Loaded Outputs

(at VDD = 3.3V)

At 48MHz, Cload=15pF

4.0

4.6

mA

Operating Voltage

1.62

3.63

V

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Output High Voltage at

CMOS level

V

Output drive current

At TTL level (3.3V)

12

17

mA

Short Circuit Current

(3.3V)

±50

mA