Preliminary

PLL600-27T/-37T

Low Power 3 Outputs XO 10MHz to 52MHz

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 1

FEATURES

• 3 CMOS outputs with OE tri-state control

• Low current consumption:

PLL600-27T: <4.5mA @ 27MHz with standard

CMOS buffer (3.3V)

PLL600-37T: <3.0mA @ 27MHz with CMOS

compatible Clipped buffer, offering

the lowest current consumption

(3.3V)

• 10 to 52MHz fundamental crystal input.

• Low phase noise (-130 dBc @ 10kHz offset).

• Low jitter (RMS): 2.5ps period jitter.

• 12mA drive capability at TTL output.

• 1.62V to 3.63V DC operation.

• Available in 8 pin SOIC.

DESCRIPTION

The PLL600-27T/-37T form a low cost family of XO

IC’s, designed to replace multiple XO solutions sav-

ing the cost and board space of clock distribution

buffers. In addition, they provide among the lowest

current on the market for the 10MHz to 52MHz

range. They accept input crystals from 10 to 52MHz

(fundamental resonant mode) and provide low phase

noise (<-130dBc at 10kHz offset at 30MHz), and very

low jitter (2.5 ps RMS period jitter) outputs.

PIN ASSIGNMENT

BLOCK DIAGRAM

XTAL

OSC

XIN/FIN

XOUT

CLK0

OE

CLK1

CLK2

1

2

3

45

6

7

8

XIN/FIN

OE^

CLK1

GND

XOUT

VDD

CLK2

CLK0

^: Denotes internal Pull-up