| 数据搜索系统,热门电子元器件搜索 |
|
PLL701-10XC-R 数据表(PDF) 3 Page - PhaseLink Corporation |
|
|
|||||||||||||||||||||||||||||
PLL701-10XC-R 数据表(HTML) 3 Page - PhaseLink Corporation |
|
3 / 8 page ![]() PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PIN/PAD DESCRIPTIONS Name Pin # Pad # Type Description XIN/FIN 1 22 I Crystal input to be connected to fundamental parallel mode crystal. (CL=20pF) or clock input. XOUT/SD0 2 23 B At power-up, this pin is acts as input pin to select the modulation rate and is latched in. After the input sampling, it is used as crystal output connector. 120k Ω internal pull up resistor. M2 3 28 I Digital control input to select output frequency. 30k Ω internal pull- up. M1 4 29 I Digital control input to select output frequency. 30k Ω internal pull- up. M0 5 30 I Digital control input to select output frequency. 30k Ω internal pull- up. SC0 6 34 I Digital control input to select spread spectrum modulation. 30k Ω internal pull-up. SC1 7 35 I Digital control input to select spread spectrum modulation. 30k Ω internal pull-up. SC2 8 1 I Digital control input to select spread spectrum modulation. 30k Ω internal pull-up. SC3 12 12 I Digital control input to select spread spectrum modulation. 30k Ω internal pull-up. FOUT 10 8 O Modulated Clock Frequency Output. The frequency before modulation is synthesized by multiplying the input frequency by 1X to 8X, depending on SD(0:1) and SC(0:3). OE 11 10 I Output Enable. When low, Tri-states all outputs. 30k Ω internal pull-up. VDD 13 13,14,15 P 3.3V Power Supply. REF/SD1 14 16 B At power-up, this pin acts as input pin to select the modulation rate and is latched in. After the input sampling, this pin provides a buffered Reference Clock Output of the same frequency as the crystal or clock input. 30k Ω internal pull-up. AVDD 15 17,18,19 P 3.3V Analog power supply. GNDOSC N/A 25 P Ground for Oscillator circuitry. GNDBUF N/A 7 P Ground for output buffer circuitry. GND 9 and 16 4,5,6,20,21 P Ground. Notes: B – bi-directional pin; I – input pin; P – power supply/ground pin. DIE SPECIFICATIONS Name Value Size 104 x 69 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |