PLL500-17B/27B/37B

Low Power CMOS Output VCXO Family (17MHz to 130MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 3

3. Voltage Control Crystal Oscillator

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

VCXO Stabilization Time *

From power valid

10

ms

VCXO Tuning Range

0V

≤ VCON ≤ 3.3V

300

ppm

CLK output pullability

VCON=1.65V,

±1.65V

±150

ppm

VCXO Tuning Characteristic

100

ppm/V

Pull range linearity

5

%

Power Supply Rejection

PWSRR

Frequency change with

VDD varied +/- 10%

-1

+1

ppm

VCON pin input impedance

2000

k

Ω

VCON modulation BW

0V

≤ VCON ≤ 3.3V, -3dB

45

kHz

Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not

production tested to any specific limits.

4. Jitter and Phase Noise Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

RMS Period Jitter

(1 sigma – 10,000 samples)

With capacitive decoupling

between VDD and GND.

2.5

ps

Phase Noise relative to carrier

@100Hz offset

-100

dBc/Hz

Phase Noise relative to carrier

@1kHz offset

-125

dBc/Hz

Phase Noise relative to carrier

@10kHz offset

-142

dBc/Hz

Phase Noise relative to carrier

@100kHz offset

-150

dBc/Hz

Phase Noise relative to carrier

@1MHz offset

-150

dBc/Hz