PLL500-27B/-37B/-47B

Low Power CMOS Output VCXO Family (27MHz to 200MHz)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 09/13/04 Page 2

PIN AND PAD DESCRIPTION

Die Pad Position

Name

Pin#

X (

µm)

Y (

µm)

Type

Description

XIN

1

94.183

768.599

I

Crystal input pin.

OE

2

94.157

605.029

I

Output Enable input pin. Disables the output when low. Internal

pull-up enables output by default if pin is not connected low.

VCON

3

94.183

331.756

I

Frequency control voltage input pin.

GND

4

94.193

140.379

P

Ground pin.

CLK

5

715.472

203.866

O

Output clock pin.

VDD

6

715.307

455.726

P

VDD power supply pin.

DRIVSEL

7

715.472

626.716

I

Output drive select pin. High drive if set to ‘0’. Low drive if set

to ‘1’. Internal pull-up.

XOUT

8

476.906

888.881

I

Crystal output pin. Ref clock input.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage Range

4.6

V

Input Voltage Range

V

Output Voltage Range

V

Soldering Temperature

240

°C

Storage Temperature

-65

150

°C

Ambient Operating Temperature

-40

+85

°C

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other

conditions above the operational limits noted in this specification is not implied.