PLL501-21/23

VCXO Clock Generator IC

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/15/01 Page 4

3. AC Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Crystal Frequency

13.5

MHz

Input Crystal Accuracy

±30

ppm

Output Clock Rise Time

0.8V ~ 2.0V

1.5

ns

Output Clock Fall Time

2.0V ~ 0.8V

1.5

ns

Output Clock Duty Cycle

Measured @ 1.4V

45

50

55

%

Max Absolute Jitter

Short Term

100

ps

Short Circuit Current

±50

mA

CLK output pullability

0V

≤VIN≤3.3V

±100

ppm

4. Voltage Control Crystal Oscillator

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

PLL Stabilization Time *

From VCXO stable

500

us

VCXO Stabilization Time *

From power valid

10

ms

Output Frequency Synthesis

Error

(Unless otherwise noted in

Frequency Table)

±30

ppm

Crystal Resonator

Frequency

Parallel Fundamental

Mode

10

13.5

15

MHz

Crystal Loading

Capacitance

14

pF

Crystal Resonator Motional

Capacitance

At cut

25

fF

VCXO Tuning Range

200

ppm

VCXO Tuning Characteristic

100

ppm/V

Note: Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits.

External Components

The PLL501-21/23 requires a minimum number of external components for proper operation. A

decoupling capacitor of 0.01

µF should be connected between VDD and GND on pin2 and 4, as close to

the PLL501-21/23 as possible. A series termination resistor of 33

Ω may be used for the clock output.

The input crystal must be connected as close to the chip as possible. The input crystal should be a

parallel mode, pullable, AT cut, 13.5MHz, with 14pF load capacitance and a C0/C1 ratio of maximum

250. Consult PhaseLink for recommended suppliers.