PLL502-39U

750kHz – 800MHz Low Phase Noise Multiplier VCXO

Universal Low Phase Noise IC’s

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 2

FREQUENCY SELECTION TABLE

SEL3

SEL2

SEL1

SEL0

Selected Multiplier

0

0

1

1

Fin x 32

0

1

1

0

Fin / 8

0

1

1

1

Fin x 2

1

0

0

1

Fin / 2

1

0

1

0

Fin / 16

1

0

1

1

Fin x 4

1

1

0

0

Fin / 4

1

1

0

1

Fin x 8

1

1

1

0

Fin x 16

1

1

1

1

No multiplication

PIN DESCRIPTIONS

Name

3x3mm QFN

Pin number

Type

Description

VCON

1

I

Voltage Control input.

GND

2,3,4,8

P

Ground connection.

CLKT

5

O

LVDS Output

VDD

6

P

+3.3V power supply.

CLKC

7

O

Complementary LVDS output

SEL1

9

I

SEL0

10

I

Multiplier selector pins. These pins have an internal pull-up that will

default SEL to ‘1’ when not connected to GND.

VDD

11

P

+3.3V power supply.

XIN

12

I

Crystal input. See Crystal Specification on page 3.

XOUT

13

I

Crystal output. See Crystal Specification on page 3.

SEL3

14

I

SEL2

15

I

Multiplier selector pins. These pins have an internal pull-up that will

default SEL to ‘1’ when not connected to GND.

OE

16

I

Output enable pin (see OE logic state table on page 1).