PLL502-39U

750kHz – 800MHz Low Phase Noise Multiplier VCXO

Universal Low Phase Noise IC’s

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 1

FEATURES

• Selectable 750kHz to 800MHz range.

• Low phase noise output (@ 10kHz frequency

offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for

155.52MHz, -115dBc/Hz for 622.08MHz).

• 12 to 25MHz crystal input.

• No external load capacitor or varicap required.

• Inverted LVDS signal Output Enable selector.

• Wide pull range (+/-200 ppm)

• Selectable 1/16 to 32x frequency multiplier.

• 3.3V operation.

• Available in 16-Pin (TSSOP or 3x3mm QFN).

DESCRIPTION

The PLL502-39U (LVDS) is a high performance and

low phase noise VCXO clock IC. It provides phase

noise performance as low as –125dBc at 10kHz off-

set (at 155MHz), by multiplying the input crystal fre-

quency up to 32x. The wide pull range (+/- 200 ppm)

and very low jitter makes this ideal for a wide range

of applications, including SONET/SDH and FEC.

PLL502-39 accepts fundamental parallel resonant

mode crystals input from 12 to 25MHz.

BLOCK DIAGRAM

PIN CONFIGURATION

(Top View)

Note: ^ designates Internal pull-up

OUTPUT ENABLE LOGICAL LEVELS

Part #

OE

State

1

Tri-state

PLL502-39U

0 (Default)

Output enabled

PLL502-39U

GND

VDD

CLKT

CLKC

12

3

4

12

11

10

9

13

14

15

16

8

7

6

5

SEL3^

XOUT

SEL2^

OE

XIN

XOUT

OE

CLKT

PLL502-39U

VCON

PLL by-pass

SEL

PLL

(Phase

Locked

Loop)

Oscillator

Amplifier

w/

integrated

varicaps

CLKC