PLL502-52

Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/17/04 Page 3

3. AC Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Crystal Frequency

20

52

MHz

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

2.4

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.2

ns

Output Clock Duty Cycle

45

50

55

%

4. Voltage Control Crystal Oscillator

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

VCXO Stabilization Time *

From power valid

10

ms

VCXO Tuning Range

0V

≤ VCON ≤ 3.3V

500

ppm

CLK output pullability

VCON=1.65V

±1.65V

±200

ppm

VCXO Tuning Characteristic

150

ppm/V

Pull range linearity

10

%

VCON input impedance

80

k

Ω

VCON modulation BW

0V

≤ VCON ≤ 3.3V, -3dB

25

kHz

Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.

5. Jitter Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period jitter RMS

20MHz

2.5

ps

Period jitter peak-to-peak

20MHz

20

ps

Integrated jitter RMS

Integrated 12 kHz to 20 MHz at 20MHz

1

ps

6. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

Phase Noise relative

to carrier

20MHz

-65

-90

-120

-140

-147

dBc/Hz

Note: Phase Noise at VCON = 0V – to be measured