PLL502-35/-37/-38/-39

750kHz – 800MHz Low Phase Noise Multiplier VCXO

Universal Low Phase Noise IC’s

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 3

PIN DESCRIPTIONS PLL502-37/-39 (see previous page of PLL502-35/-38)

Name

TSSOP

Pin number

3x3mm QFN

Pin number

Type

Description

XIN

2

12

I

Crystal input. See Crystal Specification on page 4.

XOUT

3

13

I

Crystal output. See Crystal Specification on page 4.

OE

6

16

I

Output enable pin (see OE logic state table on page 1).

VCON

7

1

I

Voltage Control input.

GND

8,9,10,14

2,3,4,8

P

Ground.

CLKT

11

5

O

True output LVDS (PLL502-39)

(N/C for PLL502-37)

CLKC

13

7

O

Complementary output LVDS (PLL502-39)

(CMOS out for PLL502-37).

SEL0

16

10

I

SEL1

15

9

I

SEL2

5

15

I

SEL3

4

14

I

Multiplier selector pins. These pins have an internal pull-up

that will default SEL to ‘1’ when not connected to GND.

VDD

1, 12

6,11

P

+3.3V power supply.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

4.6

V

Input Voltage, dc

-0.5

V

Output Voltage, dc

-0.5

V

Storage Temperature

-65

150

°C

Ambient Operating Temperature*

-40

85

°C

Junction Temperature

125

°C

Lead Temperature (soldering, 10s)

260

°C

ESD Protection, Human Body Model

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-

ditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.