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SCIMX6D4AVT08CD 数据表(PDF) 64 Page - NXP Semiconductors

部件名 SCIMX6D4AVT08CD
功能描述  i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors
PDF  170 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

SCIMX6D4AVT08CD 数据表(HTML) 64 Page - NXP Semiconductors

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i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
64
NXP Semiconductors
Electrical Characteristics
4.10
Multi-Mode DDR Controller (MMDC)
The Multi-mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.
4.10.1
MMDC Compatibility with JEDEC-Compliant SDRAMs
The i.MX 6Dual/6Quad MMDC supports the following memory types:
•
LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009
•
DDR3/DDR3L SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6Quad,
6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).
4.10.2
MMDC Supported DDR3/DDR3L/LPDDR2 Configurations
The table below shows the supported DDR3/DDR3L/LPDDR2 configurations:
4.11
General-Purpose Media Interface (GPMI) Timing
The i.MX 6Dual/6Quad GPMI controller is a flexible interface NAND Flash controller with 8-bit data
width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode, Source
Synchronous timing mode, and Samsung Toggle timing mode separately described in the following
subsections.
2 In this table:
• t means clock period from axi_clk frequency.
• CSA means register setting for WCSA when in write operations or RCSA when in read operations.
• CSN means register setting for WCSN when in write operations or RCSN when in read operations.
• ADVN means register setting for WADVN when in write operations or RADVN when in read operations.
• ADVA means register setting for WADVA when in write operations or RADVA when in read operations.
Table 43. i.MX 6Dual/6Quad Supported DDR3/DDR3L/LPDDR2 Configurations
Parameter
LPDDR2
DDR3
DDR3L
Clock frequency
400 MHz
532 MHz
532 MHz
Bus width
32-bit per channel
16/32/64-bit
16/32/64-bit
Channel
Dual
Single
Single
Chip selects
2 per channel
2
2



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