PLL520-17/-18/-19

Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4

5. Jitter Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

77.76MHz

2.5

155.52MHz

4

Period jitter RMS

622.08MHz

5

ps

77.76MHz

24

155.52MHz

29

Period jitter peak-to-peak

622.08MHz

32

ps

Integrated 12 kHz to 20 MHz at 77.76MHz

0.5

Integrated 12 kHz to 20 MHz at 155.52MHz

1.5

Integrated jitter RMS

Integrated 12 kHz to 20 MHz at 622.08MHz

1.5

ps

6. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

77.76MHz

-75

-95

-125

-145

-155

155.52MHz

-75

-95

-120

-125

-123

Phase Noise relative

to carrier

622.08MHz

-75

-95

-115

-118

-115

dBc/Hz

Note: Phase Noise measured at VCON = 0V

7. CMOS Output Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

30

mA

Output drive current

(High Drive)

30

mA

10

mA

Output drive current

(Standard Drive)

10

mA

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

2.4

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.2

ns