PLL602-38N

4x Low Phase Noise Multiplier PECL XO

Universal Low Phase Noise IC

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/24/04 Page 3

4. Jitter Specifications

PARAMETERS

CONDITIONS

FREQUENCY

MIN.

TYP.

MAX.

UNITS

Period jitter RMS

With capacitive decoupling

between VDD and GND.

Over 10,000 cycles.

100.00MHz

4.3

ps

Period jitter Peak-to-Peak

With capacitive decoupling

between VDD and GND.

Over 10,000 cycles.

100.00MHz

27

ps

Integrated jitter RMS

Integrated 12 kHz to 20 MHz

100.00MHz

2.6

4

ps

5. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

Phase Noise relative to

carrier (typical)

100.00MHz

-65

-95

-120

-125

-121

dBc/Hz

6. PECL Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

MAX.

UNITS

Output High Voltage

V

Output Low Voltage

(see figure)

V

7. PECL Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Clock Rise Time

20% to 80% of signal

300

600

ps

Clock Fall Time

80% to 20% of signal

300

600

ps

Duty Cycle

Measured @ 50% of signal

45

50

55

%

PECL Levels Test Circuit

PECL Output Skew

OUT

OUT

50

Ω

50

Ω

VDD

2.0V

50%

OUT

OUT

t

SKEW

PECL Transistion Time Waveform

DUTY CYCLE

45 - 55%

55 - 45%

OUT

OUT

50%

20%

80%

t

R

t

F