REG#

BIT(S)

BIT REF.

DESCRIPTION

6

0-3

N2[0]..N2[3]

Sets the modulus of the N2 divider.

7

0-3

N2[4]..N2[7]

The input of the N2 divider is the output of the N1 divider in all clock

modes except AUXEN.

8

3

N2[8]

8

0-2

V[0]..V[1]

Sets the gain of the VCO.

9

0-1

P[0]..P[1]

Sets the gain of the phase detector according to this table.

9

3

[P2]

Phase detector tuning bit. Normally should be set to one.

V[2]

V[1]

V[0]

VCO GAIN

(MHz/VOLT)

10

0

30

10

1

45

11

0

60

11

1

80

P[1]

P[0]

GAIN (uA/radian)

00

0.05

01

0.15

10

0.5

11

1.5

10

1

LOADEN~

Load clock divider enable (active low). When set to logic 1, the

LOAD and LD/N2 outputs will cease toggling.

10

2

SKEW-

Differential output duty factor adjust.

10

3

SKEW+

SKEW+

SKEW-

0

0

Default

0

1

100 ps

1

0

100 ps

1

1

Do not use

ICS1562B

9