ADL6316ACCZ-R7 datasheet(4/37 Pages) AD

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ADL6316

Data Sheet

Rev. 0 | Page 4 of 37

Parameter

Test Conditions/Comments

Min

Typ

Max

Units

DSA Attenuation

Range

Resolution

0.45

Gain Settling Time

Minimum attenuation to maximum attenuation

304.4

Maximum attenuation to minimum attenuation

195.0

DIGITAL LOGIC

Input Voltage

SCLK, SDI, CS, CS4, CS5, TXEN

High (VIH)

1.07

Low (VIL)

0.68

Input Current

High (IIH)

−100

μA

Low (IIL)

100

μA

Output Voltage

SDO

At 1.8 V

High (VOH)

Output high current (IOH) = −100 μA or −1 mA

static load

1.5

Low (VOL)

Output low current (IOL) = 100 μA or 1 mA static

load

0.2

At 3.3 V

High (VOH)

IOH = −100 μA or −1 mA static load

2.7

Low (VOL)

IOL = 100 μA or 1 mA static load

0.2

POWER SUPPLY

Voltage

4.75

5.0

5.25

Supply Current

High performance mode

435

Low power mode

310

Power-Down Current

DIGITAL LOGIC TIMING

Table 3.

Parameter

Description

Min

Typ

Max

Unit

fSCLK

Maximum serial clock rate, 1/tSCLK

MHz

tPWH

Minimum period that SCLK is in logic high state

tPWL

Minimum period that SCLK is in logic low state

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tDCS

Setup time between falling edge of CS and rising edge of SCLK

tDV

Maximum time delay between falling edge of SCLK and output data valid for a read operation

Timing Diagrams

R/W

A0 D7

N D60 D50

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDI

CS4 0

CS5

ADDRESS

CHIP ID

Figure 2. Serial Port Interface Register Timing, MSB First

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