MDS 613 C

1

Revision 111204

Integrated Circuit Systems, Inc.

ICS613

Description

The ICS613 is a low cost, low phase noise, high

performance clock synthesizer for any applications that

require low phase noise and low jitter. It is ICS’ lowest

phase noise multiplier. Using ICS’ patented analog and

digital Phase Locked Loop (PLL) techniques, the chip

can accept a 25MHz crystal or clock input, and

produces output clocks up to 157.5 MHz.

The chip has separate power supplies for the clock

outputs, allowing each output to be run at different

voltages. It also allows the core of the chip to operate at

3.3V, while the output clocks run at either 2.5V or 3.3V.

Features

2.5 V or 3.3 V

Block Diagram

GND

5

Reference

Divider

Phase

Comparator,

Charge Pump,

and Loop Filter

VCO

VCO

Divider

Output

Divider

S2:SO

X1/ICLK

X2

Crystal or

clock input

Capacitors must be used

with a crystal input

Crystal

Oscillator

VDDO1

VDD

2

CLK1

CLK2

VDDO2

3