8432DYI-101

www.icst.com/products/hiperclocks.html

REV. A MAY 23, 2005

1

Integrated

Circuit

Systems, Inc.

ICS8432I-101

The ICS8432I-101 is a general purpose, dual out-

put Differential-to-3.3V LVPECL high frequency

synthesizer and a member of the HiPerClockS™

family of High Performance Clock Solutions from

ICS. The ICS8432I-101 has a selectable

TEST_CLK or CLK, nCLK inputs.The TEST_CLK input accepts

LVCMOS or LVTTL input levels and translates them to 3.3V

LVPECL levels. The CLK, nCLK pair can accept most standard

differential input levels. The VCO operates at a frequency range

of 250MHz to 700MHz. The VCO frequency is programmed in

steps equal to the value of the input differential or single ended

reference frequency. The VCO and output frequency can be

programmed using the serial or parallel interfaces to the

configuration logic. The low phase noise characteristics of the

ICS8432I-101 makes it an ideal clock source for Gigabit

Ethernet and SONET applications.

• Dual differential 3.3V LVPECL outputs

• Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK

• TEST_CLK can accept the following input levels:

LVCMOS or LVTTL

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• CLK, nCLK orTEST_CLK maximum input frequency: 40MHz

• Output frequency range: 25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• Accepts any single-ended input signal on CLK input

with resistor bias on nCLK input

• Parallel interface for programming counter

and output dividers

• RMS period jitter: 5ps (maximum)

• Cycle-to-cycle jitter: 25ps (maximum)

• 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Lead-Free package fully RoHS compliant

32 31 30 29 28 27 26 25

9

10 11 12 13 14 15 16

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CLK

TEST_CLK

CLK_SEL

S_LOAD

S_DATA

S_CLOCK

MR

M5

M6

M7

M8

N0

N1

nc

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

ICS8432I-101

VCO_SEL

CLK_SEL

TEST_CLK

CLK

S_LOAD

S_DATA

S_CLOCK

nP_LOAD

M0:M8

N0:N1

VCO

PLL

FOUT0

nFOUT0

FOUT1

nFOUT1

TEST

CONFIGURATION

INTERFACE

LOGIC

÷ M

0

1

0

1

PHASE DETECTOR

÷1

÷2

÷4

÷8

MR

nCLK

HiPerClockS™

ICS