ADUCM3029-2BCPZ-R7 datasheet(36/39 Pages) AD

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ADuCM3027/ADuCM3029

Data Sheet

Rev. B | Page 36 of 39

ABOUT ADuCM3027/ADuCM3029 SILICON ANOMALIES

This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM3027/ADuCM3029. These anomalies represent

the currently known differences between revisions of the ADuCM3027/ADuCM3029 product(s) and the functionality specified in the

ADuCM3027/ADuCM3029 data sheet(s) and the Hardware Reference manual.

Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries

to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended

workarounds outlined in this section.

ADuCM30297/ADuCM3029 FUNCTIONALITY ISSUES

Silicon Revision Identifier

Silicon Status

No. of Reported Anomalies

1.2

Released

4 (21000011, 21000015, 21000016, 21000017)

A silicon revision number with the form x.y is branded on all devices. The silicon revision can be electronically determined by reading

Bits[3:0] of the SYS_CHIPID register. SYS_CHIPID = 0x4 indicates Silicon Revision 1.2.

FUNCTIONALITY ISSUES

Table 30 through Table 33 detail all known silicon anomalies for the ADuCM3027/ADuCM3029 including a description, workaround,

and identification of applicable silicon revisions.

Table 30. 21000011—I2C Master Mode Fails to Generate Clock

Background

When the I2C clock dividers are configured in master mode such that the sum of the LOW bit in the I2C_DIV register

and the HIGH bit in the I2C_DIV register is less than 16, the I2C fails to generate a clock.

Issue

The I2C master mode fails to generate clock when clock dividers are too small.

Workaround

Program the I2C clock dividers such that I2C_DIV.LOW + I2C_DIV.HIGH ≥ 16.

Related Issues

None.

Table 31. 21000015—Pin P2_11 Not Retained

Background

The state of the P2_11 pin is not retained after waking up from shutdown mode.

Issue

Pin P2_11 is not retained after shutdown wake up.

Workaround

None. To retain the pin state through shutdown, use any other GPIO pin instead of P2_11.

Related Issues

None.

Table 32. 21000016—Data Loss with I2C Automatic Clock Stretching

Background

When the I2C Rx FIFO is full and new I2C data is received, a data overflow occurs. When automatic clock stretching is

enabled, the transaction is paused by holding the SCL line low. This pause function works as expected when the

next read happens after the clock is stretched (for example, after the overflow is detected). However, if the read

occurs after the last bit of the I2C data is received but before the clock is stretched, the received data is not written

to the Rx FIFO and is lost.

Issue

Possible receive data loss with I2C automatic clock stretching.

Workaround

After I2C automatic clock stretching is enabled, read the FIFO only after the overflow flag is set in the status register

to ensure the Rx FIFO is never read at the same time the overflow is asserted.

Related Issues

None.

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