83840BH

www.icst.com/products/hiperclocks.html

REV. A JANUARY 30, 2004

4

Integrated

Circuit

Systems, Inc.

ICS83840B

DDR SDRAM MUX

t

PD

V

DD

2

V

DD

2

V

-1.25V ± 0.1V

tsk(o)

V

DD

2

V

DD

2

nDPx

nDPy

D or H

H or D

tsk(o)

V

DD

2

V

DD

2

1.25V

1.25V

1.25V

0V

2.5V

Output nDPx

(See Note)

Sn

(Low-level

enabling)

NOTE: The output is high except when disabled by the Sn control.

←

XDP0:XDP9

XDP0:XDP9

SCOPE

Qx

LVCMOS

V

DD

GND

This circuit is used for test purposes only,

not intended for application use.