84329BV

www.icst.com/products/hiperclocks.html

REV. B JANUARY 18, 2006

2

Integrated

Circuit

Systems, Inc.

ICS84329B

N output divider. On the LOW-to-HIGH transition of the

nP_LOAD input, the data is latched and the M divider remains

loaded until the next LOW transition on nP_LOAD or until a

serial event occurs. The TEST output is Mode 000 (shift reg-

ister out) when operating in the parallel input mode. The rela-

tionship between the VCO frequency, the crystal frequency

and the M divider is defined as follows:

The M value and the required values of M0 through M8

are shown in Table 3B, Programmable VCO Frequency

Function Table. Valid M values for which the PLL will

achieve lock are defined as 250

≤ M ≤ 511. The frequency

out is defined as follows:

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the

shift register are loaded into the M divider when S_LOAD tran-

sitions from LOW-to-HIGH. The M divide and N output divide

values are latched on the HIGH-to-LOW transition of S_LOAD.

If S_LOAD is held HIGH, data at the S_DATA input is passed

directly to the M divider on each rising edge of S_CLOCK.

The serial mode can be used to program the M and N bits and

test bits T2:T0. The internal registers T2:T0 determine the state

of the TEST output as follows:

NOTE: The functional description that follows describes op-

eration using a 16MHz crystal. Valid PLL loop divider values

for different crystal or input frequencies are defined in the In-

put Frequency Characteristics, Table 6, NOTE 1.

The ICS84329B features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A series-resonant, fundamental crystal is used as the

input to the on-chip oscillator. The output of the oscillator is

divided by 16 prior to the phase detector. With a 16MHz crys-

tal this provides a 1MHz reference frequency. The VCO of the

PLL operates over a range of 250MHz to 700MHz. The output

of the M divider is also applied to the phase detector.

The phase detector and the M divider force the VCO output fre-

quency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too

high or too low), the PLL will not achieve lock. The output of the

VCO is scaled by a divider prior to being sent to each of the LVPECL

output buffers.The divider provides a 50% output duty cycle.

The programmable features of the ICS84329B support two

input modes to program the M divider and N output divider.

The two input operational modes are parallel and serial. Fig-

ure 1 shows the timing diagram for each mode. In parallel mode

the nP_LOAD input is LOW. The data on inputs M0 through

M8 and N0 through N1 is passed directly to the M divider and

N

fout =

fVCO

=

16

M

fxtal x

N

Time

t

S

t

H

t

S

t

H

t

S

M, N

T2

T1

T0

N1

N0

M8

M7

M6

M5

M4

M3

M2

M1

M0

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

S_LOAD

16

M

fVCO =

fxtal

x

T2

T1

T0

TEST Output

0

0

0

Shift Register Out

0

0

1

High

0

1

0

PLL Reference Xtal ÷ 16

0

1

1

VCO ÷ M

(non 50% Duty M divider)

1

0

0

fOUT

LVCMOS Output Frequency < 200MHz

1

0

1

Low

1

1

0

S_CLOCK ÷ M

(non 50% Duty Cycle M divider)

1

1

1

fOUT ÷ 4

fOUT

fOUT

fOUT

fOUT

fOUT

fOUT

fOUT

S_CLOCK ÷ N divider

fOUT