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DCEP 数据表(PDF) 7 Page - Maxim Integrated Products |
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DCEP 数据表(HTML) 7 Page - Maxim Integrated Products |
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7 / 26 page ![]() MAX19527 Evaluation Kit ________________________________________________________________________________________ _ 7 Input/Output/Clock Tab Output Format The Output_ Format group box contains several func- tions that format the output data. The Reverse_ Bit_ Order checkbox allows the user to change the LVDS output data to a MSB-first format and displays the bit-order configuration. The Format checkbox configures the output data format to binary or two’s complement, and displays the current data format. The Test_Data_Level drop-down list gives the user the option of configuring the ADC’s OUT1–OUT8 channels to display the normal LVDS data outputs, or setting the channel’s outputs to a static high or low state. Data Test Pattern The Test_Data drop-down list gives the user the option to choose between normal and test data modes. Select Normal from the drop-down list to operate the LVDS outputs under normal conditions. In normal operation, all GUI functions in the Data_ Test_ Pattern group box (with the exception of the Test_Data drop-down list) are disabled. When Pattern is selected, all GUI functions in the Data_Test_Pattern group box become active. The Test_ Pattern drop-down list allows the user to choose between several test patterns for data-timing alignment. Selecting Normal from the Test_ Data drop- down list configures the test pattern channels according to the option selected in the Test_Data_Level drop-down list. Selecting Pattern from the Test_Data drop-down list allows the user to generate factory test and custom pat- terns at the output channels. See Table 2 for generating the IC test patterns. Three buttons (WriteCUSTOM1, WriteCUSTOM2, and WriteCUSTOM1-2) and their respective edit boxes also become active when Pattern is selected from the Test_ Data drop-down list. The buttons are available for load- ing customized 8-bit test patterns in the ADC’s 0x07, 0x08, and 0x09 registers. The registers are updated by pressing the WriteCUSTOM1, WriteCUSTOM2, or WriteCUSTOM1-2 buttons. LVDS Output Adjustments The LVDS_ Output_ Adjustments group box contains controls to set the channel OUT1–OUT8 common-mode output voltage, output current, and back termination. The CM_Adjust drop-down list sets the output driver’s common-mode voltage. The Current_Adjust drop-down list sets the output driver’s current. The Termination drop-down list sets the termination resistance. Input Common-Mode Voltage When checked, the SELF checkbox applies a common- mode voltage to the ADC’s IN_+/IN_- input pins and disables the common-mode input pins when not select- ed. The Adjust drop-down list sets the common-mode voltage according to the value selected. The selected common-mode voltage can be monitored through the CMOUT test point. When enabling SELF, verify that shunts are not installed on jumpers JU1–JU8 System Timing The Test_ FRAME_ Level drop-down list gives the user the option of configuring the ADC’s FRAME LVDS output channel to display the normal FRAME output frequency (identical to input clock frequency), or setting the FRAME output to a static high or low state. The CLK_ Controls group box contains controls for manipulating the input clock signal. The PLL_Frequency_ drop-down list programs the clock multiplier for the inter- nal PLL in order to set the sampling frequency range. Ensure that the input clock frequency, applied at the EV kit CLK SMA connector, falls between the selected minimum and maximum frequency in the drop-down list. The Output_Phase drop-down list adjusts the phase of the serial LVDS output clock (CLKOUT), relative to the output data frame. Refer to the timing diagrams in the MAX19527 IC data sheet for additional information. The Test_CLKOUT_Level drop-down list gives the user the option of configuring the ADC’s CLKOUT LVDS output channel to display the normal CLKOUT signal, or setting the output signal to a static high or low state. The 100_ Ohm_ Input_ Term checkbox switches 100I across differential clock inputs when checked. Table_2._Test_Pattern_Selection TEST_ PATTERNS OUTPUT Skew (010101010101) à repeats every frame SYNC (111111000000) à repeats every frame Custom Custom test pattern à repeats every two frames Ramp 12-bit ramp from 0 to 4095 and repeats Pseudo9 Pseudorandom data pattern (short 29 sequence) Pseudo23 Pseudorandom data pattern (long 223 sequence) |
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