USB7252C datasheet(49/63 Pages) MICROCHIP

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2021 Microchip Technology Inc.

DS00003852A-page 49

9.6

AC Specifications

This section details the various AC timing specifications of the device.

9.6.1

POWER SUPPLY AND RESET_N SEQUENCE TIMING

There is no specific requirement for power sequencing of

VDD33 and VCORE for device operation. Figure 9-2 illustrates

the recommended power supply sequencing for ensuring long term reliability of the device.

VCORE should rise after or

at the same time as

VDD33. Similarly, RESET_N should rise after or at the same time as VDD33. RESET_N does not

have any other timing dependencies. The rise times for

VCORE and VDD33 are provided in Section 9.2, Operating Con-

ditions** and Figure 9-1.

9.6.2

POWER-ON AND CONFIGURATION STRAP TIMING

Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where

RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following

timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in

Section 9.2, Operating Conditions**.

Device configuration straps are also latched as a result of

RESET_N assertion. Refer to Section 9.6.3, Reset and Con-

figuration Strap Timing for additional details.

FIGURE 9-2:

POWER SUPPLY AND RESET_N SEQUENCE TIMING

TABLE 9-4:

POWER SUPPLY AND RESET_N SEQUENCE TIMING

Symbol

Description

Min

Typ

Max

Units

tVDD33

VDD33 to VCORE rise delay

treset

VDD33 to RESET_N rise delay

FIGURE 9-3:

POWER-ON CONFIGURATION STRAP VALID TIMING

TABLE 9-5:

POWER-ON CONFIGURATION STRAP LATCHING TIMING

Symbol

Description

Min

Typ

Max

Units

tcsh

Configuration strap hold after external power supplies at opera-

tional levels

VDD33

VCORE

RESET_N

All External

Power Supplies

Vopp

Configuration

Straps

tcsh

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