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USB7216CT/KDX 数据表(PDF) 17 Page - Microchip Technology

部件名 USB7216CT/KDX
功能描述  6-Port USB 3.2 Gen 2 Type-C짰 Controller Hub
PDF  60 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

USB7216CT/KDX 数据表(HTML) 17 Page - Microchip Technology

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2021 Microchip Technology Inc.
DS00003851A-page 17
USB7216C
3.3
Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(
RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following
deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the var-
ious device configuration straps and associated programmable pin functions.
3.3.1
PORT DISABLE CONFIGURATION (
PRT_DIS_P[6:1] / PRT_DIS_M[6:1])
The
PRT_DIS_P[6:1] / PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1)
For
PRT_DIS_Px (where x is the corresponding port 6-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For
PRT_DIS_Mx (where x is the corresponding port 6-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
3.3.2
NON-REMOVABLE PORT CONFIGURATION (
CFG_NON_REM)
The
CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
six settings. These modes are selected by the configuration of an external resistor on the
CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-
up, as shown in Table 3-2.
Note:
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap
Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may
capture incorrect strap values.
Note:
Both
PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0
port.



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