Detailed Description

Reset Output

A microprocessor’s (µP’s) reset input starts the µP in a

known state. These µP supervisory circuits assert reset

to prevent code execution errors during power-up, power-

down, brownout conditions, or a watchdog timeout.

keeps RESET low for the reset timeout period; after this

interval, RESET goes high (Figure 2).

threshold), RESET goes low. Each time RESET is assert-

goes below the reset threshold, the internal timer restarts.

The watchdog timer can also initiate a reset. See the

Watchdog Input section.

The MAX804_/MAX805_ active-high RESET output is

open drain, and the inverse of the MAX690_/MAX704_/

MAX802_/MAX806_ RESET output.

Reset Threshold

The MAX690T/MAX704T/MAX805T are intended for 3.3V

systems with a ±5% power-supply tolerance and a 10%

system tolerance. Except for watchdog faults, reset will

not assert as long as the power supply remains above

3.15V (3.3V - 5%). Reset is guaranteed to assert before

the power supply falls below 3.0V.

The MAX690S/MAX704S/MAX805S are designed for

3.3V ±10% power supplies. Except for watchdog faults,

they are guaranteed not to assert reset as long as the

supply remains above 3.0V (3.3V - 10%). Reset is

guaranteed to assert before the power supply falls below

The MAX690R/MAX704R/MAX805R are optimized for

monitoring 3.0V ±10% power supplies. Reset will not

occu

guaranteed to occur before the supply falls below 2.59V

(3.0V - 14%).

The MAX802R/S/T, MAX804R/S/T, and MAX806R/S/T are

respectively similar to the MAX690R/S/T, MAX805R/S/T,

and MAX704R/S/T, but with tightened reset and power-fail

threshold tolerances.

PIN

NAME

FUNCTION

MAX690

MAX802

MAX704

MAX806

MAX804

MAX805

1

1

1

2

2

2

Main Supply Input

3

3

3

GND

Ground

4

4

4

PFI

low; otherwise, PFO remains high. Connect to ground if unused.

5

5

5

PFO

otherwise, PFO remains high. Leave open if unused.

6

—

6

WDI

Watchdog Input. If WDI remains high or low for 1.6s, the internal watchdog timer runs out

and reset is triggered. The internal watchdog timer clears while reset is asserted or when

WDI sees a rising or falling edge. The watchdog function cannot be disabled.

—

6

—

MR

Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as

MR is low and for 200ms after MR returns high. This active-low input has an internal

70µA pullup current. It can be driven from a TTL or CMOS logic line, or shorted to ground

with a switch. Leave open if unused.

7

7

—

RESET

Active-Low Reset Output. Pulses low for 200ms when triggered, and stays low whenever

goes from low to high.

—

—

7

RESET Active-High, Open-Drain Reset Output is the inverse of RESET.

8

8

8

VBATT

MAX690T/S/R, MAX704T/S/R,

MAX802T/S/R, MAX804−MAX806T/S/R

3.0V/3.3V Microprocessor

Supervisory Circuits

www.maximintegrated.com

Maxim Integrated │ 6

Pin Description