843002AGI

www.icst.com/products/hiperclocks.html

REV. A JANUARY 4, 2006

9

Integrated

Circuit

Systems, Inc.

ICS843002I

The ICS843002I has been characterized with 18pF parallel

resonant crystals. The capacitor values shown in Figure 2

below were determined using a 26.5625MHz, 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

ICS843002I

C1

33p

X1

18pF Parallel Crystal

C2

27p

XTAL_OUT

XTAL_IN

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical ter-

mination for LVPECL outputs. The two different layouts

mentioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs

that generate ECL/LVPECL compatible outputs. There-

fore, terminating resistors (DC current path to ground)

or current sources must be used for functionality. These

outputs are designed to drive 50

Ω transmission lines.

Matched impedance techniques should be used to maxi-

mize operating frequency and minimize signal distor-

tion. Figures 3A and 3B show two different layouts which

are recommended only as guidelines. Other suitable

clock layouts may exist and it would be recommended

that the board designers simulate to guarantee compat-

ibility across all printed circuit and clock component pro-

cess variations.