PCF2127A datasheet(6/86 Pages) NXP

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NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

• The register at address 05h is for software reset.

• The memory addresses 06h through to 0Dh are used as counters for the clock function

(1/100 seconds up to years). The date is automatically adjusted for months with fewer

than 31 days, including corrections for leap years. The clock can operate in 12-hour

mode with an AM/PM indication or in 24-hour mode (see Section 7.9).

• The registers at addresses 0Eh through 12h define the alarm function. It can be

selected that an interrupt is generated when an alarm event occurs (see Section 7.10).

• The register at address 13h defines the temperature measurement period and the

clock out mode. The temperature measurement can be selected from every 32 minutes

(default) down to every 4minutes (see Table 17). CLKOUT frequencies of 32.768 kHz

(default) down to 1 Hz for use as system clock, microcontroller clock, and so on, can be

chosen (see Table 18).

• The registers at addresses 14h to 2Fh are used for the timestamp function. When

the trigger event happens, the actual time is saved in the timestamp registers (see

Section 7.12).

• The register at address 30h is used for the correction of the crystal aging effect (see

Section 7.4.1).

• The registers at addresses 31h to 34h are used for interrupt configration.

• The registers at addresses 35h and 36h are used for the watchdog timer functions. The

watchdog timer has four selectable source clocks allowing for timer periods from less

than 20 ms to greater than 4 hours (see Table 59). An interrupt is generated when the

watchdog times out.

• The registers 100th Seconds, Seconds, Minutes, Hours, Days, Months, and Years

are all coded in Binary Coded Decimal (BCD) format to simplify application use. Other

registers are either bit-wise or standard binary.

When one of the RTC registers is written or read, the content of all counters is

temporarily frozen, all registers hold their state during SPI or I2C transactions. The

time stamp registers would update as soon as the bus transaction completes. This

prevents a faulty writing or reading of the clock and calendar during a carry condition

(see Section 7.9.9).

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

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