ICS3002AI01L datasheet(1/15 Pages) ICST

部件名	ICS3002AI01L

功能描述	FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

PDF	15 Pages

Scroll/Zoom	100%

制造商	ICST [Integrated Circuit Systems]

网页	http://www.icst.com

标志

1 / 15 page

843002AGI-01

www.icst.com/products/hiperclocks.html

REV. A JANUARY 6, 2006

1

Integrated

Circuit

Systems, Inc.

ICS843002I-01

FEMTOCLOCKS™CRYSTAL-TO-

3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

GENERAL DESCRIPTION

The ICS843002I-01 is a 2 output LVPECL

synthesizer optimized to generate Ethernet

reference clock frequencies and is a member

of the HiPerClocksTM family of high perfor-

mance clock solutions from ICS. Using a

25MHz 18pF parallel resonant crystal, the following

frequencies can be generated based on the 2 frequency

select pins (F_SEL[1:0]): 156.25MHz, 125MHz, and

62.5MHz. The ICS843002I-01 uses ICS’ FemtoClockTM

low phase noise VCO technology and can achieve 1ps

or lower typical rms phase jitter, easily meeting Ethernet

jitter requirements. The ICS843002I-01 is packaged in a

small 20-pin TSSOP package.

FEATURES

• Two 3.3V or 2.5V LVPECL outputs

• Selectable crystal oscillator interface

or LVCMOS/LVTTL single-ended input

• Supports the following output frequencies:

156.25MHz, 125MHz and 62.5MHz

• VCO range: 560MHz - 680MHz

• RMS phase jitter @ 156.25MHz, using a 25MHz crystal

(1.875MHz-20MHz): 0.55ps (typical)

• Output skew: 30ps (maximum)

• Supply Voltage Modes

Core/Outputs

3.3/3.3

2.5/2.5

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS-compliant

packages

HiPerClockS™

ICS

PIN ASSIGNMENT

1

0

1

0

Phase

Detector

VCO

625MHz

(w/25MHz

Reference)

M = 25 (fixed)

F_SEL[1:0]

0 0

÷4 (default)

0 1

÷5

1 0

÷10

1 1

÷5

OSC

2

ICS843002I-01

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm

package body

G Package

Top View

BLOCK DIAGRAM

FREQUENCY SELECT FUNCTION TABLE

F_SEL[1:0]

nPLL_SEL

REF_CLK

XTAL_IN

XTAL_OUT

nXTAL_SEL

MR

Q0

nQ0

Q1

nQ1

Pulldown

25MHz

nc

VCCO

Q0

nQ0

MR

nPLL_SEL

nc

VCCA

F_SEL0

VCC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VCCO

Q1

nQ1

VEE

VCC

nXTAL_SEL

REF_CLK

XTAL_IN

XTAL_OUT

F_SEL1

Pulldown

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H

M

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F0

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1

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