MDS 671-06 D

4

Revision 050405

www.icst.com

ICS671-06

AC Electrical Characteristics

VDD = 3.3 V ±5%

Note 1: With CLKIN = 100MHz, FBIN to CLKA4, all outputs at 100 MHz.

Note 2: When there is no clock signal present at CLKIN, the ICS671-06 will enter power down mode. The

PLL is stopped and the outputs are tri-state.

Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN.

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Output High Voltage,

CMOS level

VDD-0.4

V

Operating Supply Current

IDD

No Load, S2 = 1, S1 = 1,

Note 1

35

mA

Power Down Supply

Current

IDD

CLKIN = 0, S2 = 0, S1 = 1

12

µA

CLKIN = 0, Note 2

12

µA

Short Circuit Current

Each output

±50

mA

Input Capacitance

S2, S1, FBIN

5

pF

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

Input Clock Frequency

See table on page 2

10

133

MHz

Output Clock Frequency

See table on page 2

10

133

MHz

Output Rise Time

0.8 to 2.0 V, CL = 30 pF

2.5

ns

Output Fall Time

2.0 to 0.8 V, CL = 30 pF

2.5

ns

Output Clock Duty Cycle

Measured at VDD/2

45

50

55

%

Device to Device Skew

Rising edges at VDD/2

700

ps

Output to Output Skew

Rising edges at VDD/2

200

ps

Input to Output Skew

Rising edges at VDD/2, FBIN to

CLKA4, S1 = 1, S0 = 1, Note 1

±250

ps

Maximum Absolute JItter

130

200

ps

Cycle to Cycle Jitter

30 pF, measured at 66.67M

200

ps

15 pF, measured at 66.67M

200

ps

15 pF, measured at 133.33M

100

ps

PLL Lock Time

Note 3

1.0

ms