844004AGI-04

www.icst.com/products/hiperclocks.html

REV. A JANUARY 26, 2006

9

Integrated

Circuit

Systems, Inc.

ICS844004I-04

PRELIMINARY

Figure 4 shows a schematic example for ICS844004i-04. In this

example, the input is a 19.44MHz parallel resonant crystal with

load capacitor CL=18pF. The 22pF frequency fine tuning

capacitors are used C1 and C2.This example also shows general

logic control input handling. For decoupling capacitors, it is

recommended to have one decouple capacitor per power pin.

C6

0.1u

VCCO

C9

0.1u

RD2

1K

R2

10

+

-

Logic Control Input Examples

Zo = 50 Ohm

Zo = 50 Ohm

RD1

Not Install

C1

27pF

RU1

1K

R3

100

VCC

VCCO

C7

0.1u

VCC

RU2

Not Install

X1

19.44MHz

C2

33pF

VCC

To Logic

Input

pins

U1

844004i-04

+

-

Set Logic

Input to

'0'

VCC

C8

0.1u

R4

100

VCCO=3.3V

Zo = 50 Ohm

Set Logic

Input to

'1'

18pF

To Logic

Input

pins

C4

0.01u

VCCA

C3

10uF

VCC=3.3V

Zo = 50 Ohm

Each decoupling capacitor should be located as close as

possible to the power pin. The low pass filter R2, C3 and C4

should also be located as close to the VCCA pin as possible.

For LVDS driver, the unused output pairs should be terminated

with a 100

Ω resistor across.