MP7651

9

Rev. 2.00

Figure 5. MC68000 Interface (Simplified Diagram)

MC68000

A0 to A23

AS

VMA

VPA

VDS

DB0 to DB15

ADDRESS

DECODER

CS

1/4 7HC125

CLK

LD

SDI

RST

DB0

FROM SYSTEM RESET

DATA BUS

16

16

ADDRESS BUS

ADDRESS BUS

DATA BUS

MC6800

A0 to A15

02

R/W

DB0 to DB7

Figure 6. MC6800 Interface (Simplified Diagram)

16

3

16

A0 to A2

E1

E3

E2

ADDRESS

DECODER

74LS138

DB7

SDI

CLK

LD

RST

FROM SYSTEM RESET

88

NOTES:

1.

Execute consecutive memory write instructions while manipulating the data between WRITEs so that

each WRITE presents the next bit

2.

The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE

location 2000, R/W, and 02. A WRITE to address 4000 transfers data from the input shift register to the

DAC register.

4

CS0P to CS3P

4

CS0P to CS3P

MP7651

MP7651