TC9328AF datasheet(21/84 Pages) TOSHIBA

21 / 84 page

TC9328AF

2002-02-07

Machine Language (16 bits)

Instruc

-tion

Group

Mnemonic

Skip

Function

Description

Operation

Description

(6 bits)

(2 bits)

(4 bits)

SHRC

Shift memory bits to

right direction with

carry

→ (M) b3 → (M) b2 →

(M) b1

→ (M) b0→ (CY)

111111

0000

RORC

Rotate memory bits

to right direction with

carry

(M) b3

→ (M) b2 →

(M) b1

→ (M) b0 →

(CY)

111111

0001

XCH

Exchange memory

bits mutually

(M) b3

⇔ (M) b0,

(M) b2

⇔ (M) b1

111111

0110

DAL

ADDR3, r

IF DAL bit

= 0 then

load program in page

0 to DATA register

(Note)

IF DAL bit

= 1 then

load program

memory referring to

DAL address register

to DATA register

(Note)

DATA

← [ADDR3 + (r)] p

in page 0

111110

ADDR3 (6 bits)

At P

= “0” H, the

condition is CPU

waiting

(Soft wait mode)

WAIT

At P

= “1” H, expect

for clock generator,

all function is waiting

(Hard wait mode)

Wait at condition P

111111



0100

CKSTP

Clock generator stop

Stop clock generator to

MODE condition

111111



0101

NOOP

No operation



111111



1111

Note: The lower four bits among the ten-bit address of the program memory specified with the DAL instruction (DAL

ADDR3 and r) are addressed indirectly with the contents of the general registerer.

Note: The excution period for the DAL instruction is two machine cycles

Note: DAL bit and DAL address register (DA) are arranged on I/O map.

(

→ Refer to the register port item)

Note: When “1” is set to DAL bit and DAL instruction is executed, all the operand part becomes invalid and reference

address is used for DAL address register (DA). In this case, assign 0, 0 as dummy data for the operand.

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