MAX30002 datasheet(21/44 Pages) MAXIM

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SPI Interface Description

32 Bit Normal Mode Read/Write Sequences

The MAX30002 interface is SPI/QSPI/Micro-wire/DSP

compatible. The operation of the SPI interface is shown

in Figure 1a. Data is strobed into the MAX30002 on SCLK

rising edges. The device is programmed and accessed by

a 32 cycle SPI instruction framed by a CSB low interval.

The content of the SPI operation consists of a one byte

command word (comprised of a seven bit address and a

Read/Write mode indicator, i.e., A[6:0] + R/W) followed by

a three-byte data word. The MAX30002 is compatible with

CPOL = 0/CPHA = 0 and CPOL = 1/CPHA = 1 modes of

operation.

Write mode operations will be executed on the 32nd SCLK

rising edge using the first four bytes of data available. In

write mode, any data supplied after the 32nd SCLK rising

edge will be ignored. Subsequent writes require CSB to

de-assert high and then assert low for the next write com-

mand. In order to abort a command sequence, the rise

of CSB must precede the updating (32nd) rising-edge of

SCLK, meeting the tCSA requirement.

Read mode operations will access the requested data

on the 8th SCLK rising edge, and present the MSB of

the requested data on the following SCLK falling edge,

allowing the µC to sample the data MSB on the 9th SCLK

rising edge. Configuration, Status, and FIFO data are all

available via normal mode read back sequences. If more

than 32 SCLK rising edges are provided in a normal read

sequence then the excess edges will be ignored and the

device will read back zeros.

If accessing the STATUS register or the BIOZ FIFO mem-

ory, all interrupt updates will be made and the internal

FIFO read pointer will be incremented in response to the

30th SCLK rising edge, allowing for internal synchroniza-

tion operations to occur. See the data tag structures used

within the FIFO for means of detecting end-of-file (EOF)

samples, invalid (empty samples) and other aides for

efficiently using and managing normal mode read back

operations.

Burst Mode Read Sequence

The MAX30002 provides commands to read back the

BIOZ FIFO memory in a burst mode to increase data

transfer efficiency. Burst mode uses different regis-

ter addresses than the normal read sequence register

addresses. The first 32 SCLK cycles operate exactly as

described for the normal mode. If the µC continues to

provide SCLK edges beyond the 32nd rising edge, the

MSB of the next available FIFO word will be presented

on the next falling SCLK edge, allowing the µC to sample

the MSB of the next word on the 33rd SCLK rising edge.

Any affected interrupts and/or FIFO read pointers will be

incremented in response to the (30+nx24)th SCLK rising

edge where n is an integer starting at 0. (i.e., on the 30th,

54th, and 78th SCLK rising-edges for a three-word, burst-

mode transfer).

This mode of operation will continue for every 24 cycle

sub frame, as long as there is valid data in the FIFO. See

the data tag structures used within each FIFO for means

of detecting end-of-file (EOF) samples, invalid (empty

samples) and other aides for efficiently using and manag-

ing burst mode read back operations.

There is no burst mode equivalent in write mode.

MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

www.maximintegrated.com

Maxim Integrated │ 21

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