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AT90USB646 数据表(PDF) 21 Page - ATMEL Corporation |
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AT90USB646 数据表(HTML) 21 Page - ATMEL Corporation |
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21 / 434 page ![]() 21 7593A–AVR–02/06 AT90USB64/128 Figure 5-2. Data Memory Map 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 5-3. 32 R egisters 64 I/O R egisters I nternal S RAM (8192 x 8) $0000 - $001F $0020 - $005F $FFFF $0060 - $00FF D ata Memory E xternal S RAM (0 - 64K x 8) 160 E xt I/O R eg. XMem start ISRAM end ISRAM start |
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