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Z8F082ASH020SC 数据表(PDF) 39 Page - Zilog, Inc. |
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Z8F082ASH020SC 数据表(HTML) 39 Page - Zilog, Inc. |
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39 / 244 page ![]() PS024705-0405 P R E L I M I N A R Y Reset and STOP Mode Recovery Z8 Encore! XP® F08xA Series Product Specification 21 Power-On Reset Each device in the Z8 Encore! XP® F08xA Series contains an internal Power-On Reset (POR) circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level. After the supply voltage exceeds the POR voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has timed out. If the crystal oscillator is enabled by the option bits, this tim- eout is longer. After the ZZ8 Encore! XP® F08xA Series device exits the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Watch- Dog Timer Control (WDTCTL) register is set to 1. Figure 4 illustrates Power-On Reset operation. Refer to the “Electrical Characteristics” on page 191 for the POR threshold voltage (VPOR). Table 9. Reset Sources and Resulting Reset Type Operating Mode Reset Source Special Conditions NORMAL or HALT modes Power-On Reset / Voltage Brown- Out Reset delay begins after supply voltage exceeds POR level Watch-Dog Timer time-out when configured for Reset None RESET pin assertion All reset pulses less than three system clocks in width are ignored. On-Chip Debugger initiated Reset (OCDCTL[0] set to 1) System Reset, except the On-Chip Debugger is unaffected by the reset STOP mode Power-On Reset / Voltage Brown- Out Reset delay begins after supply voltage exceeds POR level RESET pin assertion All reset pulses less than the specified analog delay are ignored. See “Electrical Characteristics” on page 191. DBG pin driven Low None |
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