Z8F042APH020SC datasheet(13/276 Pages) ZILOG

13 / 276 page

PS022815-0206

List of Figures

Z8 Encore! XP® 4K Series

Product Specification

xiii

List of Figures

Figure 1. Z8 Encore! XP® 4K Series Block Diagram . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Z8F04xA, Z8F02xA, and Z8F01xA in 8-Pin SOIC, QFN/MLF-S, or PDIP

Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Z8F04xA, Z8F02xA, and Z8F01xA in 20-Pin SOIC, SSOP or PDIP Pack-

age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Z8F04xA, Z8F02xA, and Z8F01xA in 28-Pin SOIC, SSOP or PDIP Pack-

age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 8. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 9. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 10. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 11. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . 91

Figure 12. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . 91

Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format . . . 95

Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)

Figure 15. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . 99

Figure 16. Infrared Data Communication System Block Diagram . . . . . . . . . 109

Figure 17. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 18. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 19. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . 114

Figure 20. Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 21. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 22. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . 139

Figure 23. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface

(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

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