Z8F021ASH020EC datasheet(78/276 Pages) ZILOG

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PS022815-0206

Interrupt Controller

Z8 Encore! XP® 4K Series

Product Specification

PA7VENL—Port A Bit[7] or LVD Interrupt Request Enable Low Bit

PA6CENL—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit

PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit

IRQ2 Enable High and Low Bit Registers

Table 43 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-

isters (Tables 44 and 45) form a priority encoded enabling for interrupts in the Interrupt

Request 2 register.

Reserved—Must be 0.

C3ENH—Port C3 Interrupt Request Enable High Bit

C2ENH—Port C2 Interrupt Request Enable High Bit

Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL)

BITS

FIELD

PA7VENL PA6CENL

PA5ENL

PA4ENL

PA3ENL

PA2ENL

PA1ENL

PA0ENL

RESET

000

R/W

R/WR/W

ADDR

FC5H

Table 43. IRQ2 Enable and Priority Encoding

IRQ2ENH[x]IRQ2ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Medium

Level 3

High

where x indicates the register bits from 0–7.

Table 44. IRQ2 Enable High Bit Register (IRQ2ENH)

BITS

FIELD

Reserved

C3ENH

C2ENH

C1ENH

C0ENH

RESET

000

R/W

R/WR/W

ADDR

FC7H

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