ZLP12840P2864G datasheet(39/58 Pages) ZILOG

39 / 58 page

PS024406-0106

P R E L I M I N A R Y

Memory and Registers

ZLP12840 OTP MCU

Product Specification

Memory and Registers

The Z8 LXM CPU used in the ZLP12840 family of devices incorporates special features

to extend the available memory space while maintaining the benefits of a Z8® CPU core in

consumer and battery-operated applications.

OTP Program/Constant Memory

The ZLP12840 family of devices can address up to 128KB of one-time programmable

(OTP) memory, used for object code (program instructions and immediate data) and con-

stant data (ROM tables and data constants). The amount of OTP implemented depends on

the specific device. The OTP memory space is organized in 64KB pages with the follow-

ing characteristics:

Page 0 can contain up to 64KB of program instructions and constant data. The first 12

bytes of Page 0 are reserved for the six available 16-bit interrupt request (IRQ) vectors.

Upon reset, program execution begins at address 000Ch in Page 0. Execution rolls over to

the bottom of Page 0 if the program counter exceeds the highest Page 0 address (FFFFh).

Page 1, if implemented, can contain up to 64KB of data constants and tables only. Page 1

cannot contain program instructions or immediate data. Constant data in either page can

be accessed only by the Load Constant (LDC and LDCI) instructions. LDC and LDCI use

16-bit addresses to access OTP memory.

For example, if a ZLP12840 family device contains 96KB of OTP memory, only the first

64KB (Page 0) can contain object code; the remaining 32KB (in Page 1) is available for

constant data. For a ZLP12840 family device with 64KB or less of total OTP memory, all

OTP memory is available for object code or constant data.

The page accessed by LDC or LDCI depends on the value of Program Memory Page Reg-

ister bit 0 (PMPR[0]). Page 0 is accessed if PMPR[0]=0; Page 1 is accessed if

PMPR[0]=1. PMPR[7] enables the page toggle feature. For example, if PMPR[0]=0,

PMPR[7]=1, and a Load Constant and Increment (LDCI) instruction address increments

past FFFFh, the state of PMPR[0] is toggled from 0 to 1, and the next LDCI instruction

addresses 0000h on Page 1.

Figure 8 on page 29 illustrates the Program/Constant memory map for a 128KB device.

ZLP12840P2864G 数据表(PDF) 39 Page - Zilog, Inc.