Functional Description

The ’ACT823 consists of nine D-type edge-triggered flip-

flops These have TRI-STATE outputs for bus systems or-

ganized with inputs and outputs on opposite sides The buff-

ered clock (CP) and buffered Output Enable (OE) are com-

mon to all flip-flops The flip-flops will store the state of their

individual D inputs that meet the setup and hold time re-

quirements on the LOW-to-HIGH CP transition With OE

LOW the contents of the flip-flops are available at the out-

puts When OE is HIGH the outputs go to the high imped-

ance state Operation of the OE input does not affect

the state of the flip-flops In addition to the Clock and Output

Enable pins there are Clear (CLR) and Clock Enable (EN)

pins These devices are ideal for parity bus interfacing in

high performance systems

When CLR is LOW and OE is LOW the outputs are LOW

When CLR is HIGH data can be entered into the flip-flops

When EN is LOW data on the inputs is transferred to the

outputs on the LOW-to-HIGH clock transition When the EN

is HIGH the outputs do not change state regardless of the

data or clock input transitions

Function Table

Inputs

Internal

Output

Function

OE

CLR

EN

CP

D

Q

O

HX

L

L

L

L

Z

High Z

HX

L

L

H

H

Z

High Z

H

L

X

X

X

L

Z

Clear

L

L

X

X

X

L

L

Clear

H

H

H

X

X

NC

Z

Hold

L

H

H

X

X

NC

NC

Hold

HH

L

L

L

L

Z

Load

HH

L

L

H

H

Z

Load

LH

L

L

L

L

L

Load

LH

L

L

H

H

H

Load

Logic Diagram

TLF9894 – 5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

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