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MAX96708 数据表(PDF) 14 Page - Maxim Integrated Products

部件名 MAX96708
功能描述  14-Bit GMSL Deserializer with Coax or STP Cable Input
PDF  68 Pages
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制造商  MAXIM [Maxim Integrated Products]
网页  https://www.maximintegrated.com/en.html
标志 MAXIM - Maxim Integrated Products

MAX96708 数据表(HTML) 14 Page - Maxim Integrated Products

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(VDVDD = VAVDD = 1.7 to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground, TA = -40°C to
+115°C, Typical values are at, VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
START Condition Hold Time
tHD:STA
fSCL range, Low
4
µs
fSCL range, Mid
0.6
fSCL range, High
0.26
Low Period of SCL Clock
tLOW
fSCL range, Low
4.7
µs
fSCL range, Mid
1.3
fSCL range, High
0.5
High Period of SCL Clock
tHIGH
fSCL range, Low
4
µs
fSCL range, Mid
0.6
fSCL range, High
0.26
Repeated START Condition
Setup Time
tSU:STA
fSCL range, Low
4.7
µs
fSCL range, Mid
0.6
fSCL range, High
0.26
Data Hold Time
tHD:DAT
fSCL range, Low
0
ns
fSCL range, Mid
0
fSCL range, High
0
Data Setup Time
tSU:DAT
fSCL range, Low
250
ns
fSCL range, Mid
100
fSCL range, High
50
Setup Time for STOP
Condition
tSU:STO
fSCL range, Low
4
µs
fSCL range, Mid
0.6
fSCL range, High
0.26
Bus Free Time
tBUF
fSCL range, Low
4.7
µs
fSCL range, Mid
1.3
fSCL range, High
0.5
Data Valid Time
tVD:DAT
fSCL range, Low
3.45
µs
fSCL range, Mid
0.9
fSCL range, High
0.45
Data Valid Acknowledge Time
tVD:ACK
fSCL range, Low
3.45
µs
fSCL range, Mid
0.9
fSCL range, High
0.45
Pulse Width of Spikes
Suppressed
tSP
fSCL range, Low
50
ns
fSCL range, Mid
50
fSCL range, High
50
Capacitive load each bus line
CB
100
pF
AC Electrical Characteristics (continued)
www.maximintegrated.com
Maxim Integrated │ 14
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input



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