ADN8835ACPZ-R7 datasheet(24/27 Pages) AD

24 / 27 page

ADN8835

Data Sheet

Rev. B | Page 24 of 27

Connect the ground side of the capacitor in the LC filter as close as

possible to PGNDS to minimize the ESL in the return path.

Linear Power Stage Layout Guidelines

The linear power stage consists of a MOSFET pair that forms a

linear amplifier, which operates in linear mode for very low output

currents, and changes to fully enhanced mode for greater

output currents.

Because the linear power stage does not switch currents rapidly

like the PWM power stage, it does not generate noise currents.

However, the linear power stage still requires a minimum

amount of bypass capacitance to decouple its input.

Place a 100 nF capacitor that connects from PVINL to PGNDL

as close as possible to the PVINL pin.

Placing the Thermistor Amplifier and PID Components

The thermistor conditioning and PID compensation amplifiers

work with very small signals and have gain; therefore, attention

must be paid when placing the external components with these

circuits.

Place the thermistor conditioning and PID circuit components

close to each other near the inputs of Chopper 1 and Chopper 2.

Avoid crossing paths between the amplifier circuits and the

power stages to prevent noise pickup on the sensitive nodes.

Always reference the thermistor to AGND to have the cleanest

connection to the amplifier input and to avoid any noise or

offset buildup.

EXAMPLE PCB LAYOUT USING TWO LAYERS

Figure 41, Figure 42, and Figure 43 show an example ADN8835

PCB layout that uses two layers. This layout example achieves a

small solution size of approximately 20 mm2 with all of the

conditioning circuitry and PID included. Using more layers and

blinds via allows the solution size to be reduced even further

because more of the discrete components can relocate to the

bottom side of the PCB.

Figure 41. Example PCB Layout Using Two Layers (Top and Bottom Layers)

SW _OUT

0402

R P

0201

R I

0201

C D

0201

C F

0201

VTEC

PGND

TEMPSE T

VIN

TEC+

TEC–

0402

AGND

1.0

NTC

3.0

ITEC

5.0

6.0

7.0

8.0

9.0

10.0

2.0

4.0

UNITS = (mm)

LDR

IN2N

VLIM/SD

PVINS

PVINL

OUT2

ILIM

VREF

VDD

ADN8835

PVINS

PVINL

DNC

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ADN8835ACPZ-R7 数据表(PDF) 24 Page - Analog Devices

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