ADP5091ACPZ-2-R7 datasheet(17/28 Pages) AD

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Data Sheet

ADP5091/ADP5092

Rev. A | Page 17 of 28

The typical MPPT ratio depends on the type of harvester. For

example, it is 0.7 to 0.85 for PV cells, and 0.5 for TEGs. The

sampling OCV rate is adjustable depending on the previously

sampled OCV level. To disable the MPPT function, leave the

MPPT pin floating and set the CBP pin to an external voltage

reference lower than the VIN voltage.

MINIMUM OPERATION THRESHOLD FUNCTION

By setting the MINOP pin voltage lower than the MINOP

operation voltage range of the dynamic MPPT sensing mode

(VMINOP_DSM) through a resistor to AGND, the minimum operation

threshold function can disable the main boost regulator to prevent

discharging the storage element when the energy generated by the

harvester is less than the system consumption. When the voltage

of the CBP pin decreases to the threshold set by the resistor at

the MINOP pin, the boost regulator stops switching. The

typical MINOP bias current is 2.00 µA. The minimum operation

threshold function disables the MPPT function to achieve the

sleeping quiescent current of 390 nA (typical). Disable this

function by connecting the MINOP pin to the AGND pin.

The low light density (LLD) indicator (ADP5091 only) is the

MINOP comparator output that signals the microprocessor to

calculate the cycle with insufficient input energy in a certain

period.

DISABLING BOOST

For noise or electromagnetic interference (EMI) sensitive

applications, pull the DIS_SW pin high to stop the boost

switcher temporarily to prevent interference with RF circuits.

Pull the DIS_SW pin low to resume the boost switching. The

transition delay is 1 µs (typical).

REGULATED OUTPUT WORKING MODE

The 150 mA regulated output of the ADP5091/ADP5092 not

only operates in the hysteresis boost mode or the LDO mode

but also operates in the hybrid mode in which the regulator can

smoothly transition between these two modes automatically.

After the BAT voltage exceeds the SETSD threshold or the SYS

voltage is greater than SETPG threshold, the regulator can be

enabled.

In hysteresis boost mode, the boost regulator in the ADP5091/

ADP5092 charges the output voltage slightly higher than its

preset output voltage. When the output voltage increases until

the output sense signal exceeds the hysteresis comparator upper

threshold (the sleep threshold), the regulator enters sleep mode. In

sleep mode, to allow a low quiescent current as well as high

efficiency performance, the low-side and high-side switches

and a majority of the circuitry are disabled.

During sleep mode, the output capacitor supplies the energy into

the load, the output voltage decreases until it falls below the

hysteresis comparator lower threshold (the wake threshold),

and the boost regulator wakes up and generates the pulse-width

modulation (PWM) pulses to charge the output again. The

hysteresis mode allows the regulator to act as the keep alive

power supply.

In LDO mode, the output generates power from the SYS pin

with at least a small 4.7 µF ceramic output capacitor. Using new

innovative design techniques, the LDO provides ultralow quiescent

current and superior transient performance for digital and RF

applications, and supports noise sensitive applications.

In hybrid mode, the VIN and SYS pins both extract energy to

the REG_OUT pin. When the load power is lower than the input

power, the regulator exits LDO mode and obtains the energy

only from the input side.

REG_D0 AND REG_D1

The REG_D0 and REG_D1 pins allow flexible configuration of

the working mode of the regulated output. Table 6 details the

working mode configuration set by these two pins.

Table 6. Regulated Output Working Mode Configuration

Working Mode

REG_D0

REG_D1

Boost Disable

Low

Not applicable

Boost Enable

High

Not applicable

LDO Disable

Not applicable

Low

LDO Enable

Not applicable

High

REGULATED OUTPUT CONFIGURATION

The 150 mA regulated output of the ADP5091/ADP5092 is

available in eight fixed output voltage options ranging from

1.5 V to 3.6 V by connecting one resistor through the VID pin

to the AGND pin. Table 7 shows the output voltage options set by

the VID pin.

Table 7. Output Voltage Options Set by the VID Pin

VID Configuration

Output Voltage Set by the VID Pin

Short to Ground

Programmed with external resistors

Floating

VOUT = 2.5 V

RVID = 7 kΩ

VOUT = 1.5 V

RVID = 14 kΩ

VOUT = 1.8 V

RVID = 27.7 kΩ

VOUT = 3.6 V

RVID = 55.6 kΩ

VOUT = 3.3 V

RVID = 111 kΩ

VOUT = 2.0 V

RVID = 221 kΩ

VOUT = 3.0 V

RVID = 442 kΩ

VOUT = 2.8 V

The external resistor divider or the VID pin can program the

regulated output. The ratio of the two external resistors sets the

adjustable output voltage range of 1.5 V to 3.6 V, as shown in

Figure 47. The device acts as a servo to the output to maintain

the voltage at the REG_FB pin at 1.0 V referenced to ground.

The current in R1 is then equal to 1.0 V/R2, and the current in

R1 is the current in R2 plus the REG_FB pin bias current.

Calculate the output voltage by

VOUT = 1.02 V × (1 + R1/R2)

(2)

where:

VOUT = VREG_OUT.

See Figure 47 for R1 and R2.

To minimize quiescent current, it is recommended to use large

resistance values for R1 and R2.

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