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ADP5350ACPZ-1-R7 数据表(PDF) 11 Page - Analog Devices |
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ADP5350ACPZ-1-R7 数据表(HTML) 11 Page - Analog Devices |
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11 / 63 page  Data Sheet ADP5350 Rev. B | Page 11 of 63 I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 6. Parameter Symbol Min Typ Max Unit I2C-COMPATIBLE INTERFACE Capacitive Load, Each Bus Line CS 400 pF SCL Clock Frequency fSCL 400 kHz High Time tHIGH 0.6 µs Low Time tLOW 1.3 µs Data Setup Time tSU,DAT 100 ns Hold Time1 tHD,DAT 0 0.9 µs Setup Time for Repeated Start tSU,STA 0.6 µs Hold Time for Start/Repeated Start tHD,STA 0.6 µs Bus Free Time Between a Stop and a Start Condition tBUF 1.3 µs Setup Time for Stop Condition tSU,STO 0.6 µs SCL/SDA Rise Time tR 300 ns Fall Time tF 300 ns Pulse Width of Suppressed Spike tSP 0 50 ns 1 A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 3, the I2C timing diagram. Timing Diagram Figure 3. I2C Timing Diagram S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION tLOW tSU,DAT tR tHD,DAT tSU,STA tSU,STO tSP tR tBUF tHIGH S Sr P S SDA SCL tF tHD,STA tF |
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