MWPR1124ZVHT datasheet(7/86 Pages) NXP

7 / 86 page

• 26 and 32 MHz supported for Bluetooth LE

• Bluetooth Low Energy ver. 4.2 Link Layer hardware with 2 independent

hardware connection engines

3.3 Microcontroller features

Arm Cortex-M0+ CPU

• Up to 48 MHz CPU

• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline

microarchitecture for reduced power consumption and improved architectural

performance (cycles per instruction)

• Supports up to 32 interrupt request sources

• Binary compatible instruction set architecture with the Cortex-M0 core

• Thumb instruction set combines high code density with 32-bit performance

• Serial Wire Debug (SWD) reduces the number of pins required for debugging

• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using

system RAM as the destination memory

Nested Vectored Interrupt Controller (NVIC)

• 32 vectored interrupts, 4 programmable priority levels

• Includes a single non-maskable interrupt

Wake-up Interrupt Controller (WIC)

• Supports interrupt handling when system clocking is disabled in low power

modes

• Takes over and emulates the NVIC behavior when correctly primed by the NVIC

on entry to very-deep-sleep

• A rudimentary interrupt masking system with no prioritization logic signals for

wake-up as soon as a non-masked interrupt is detected

Debug Controller

• Two-wire Serial Wire Debug (SWD) interface

• Hardware breakpoint unit for 2 code addresses

• Hardware watchpoint unit for 2 data items

• Micro Trace Buffer for program tracing

On-Chip Memory

• Up to 512 KB Flash

Feature Descriptions

MWPR1124ZVHT/MWPR1024IZVHT Data Sheet, Rev. 0, 04/2018

NXP Semiconductors

MWPR1124ZVHT 数据表(PDF) 7 Page - NXP Semiconductors

MWPR1124ZVHT 数据表(HTML) 7 Page - NXP Semiconductors

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