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ML2250 数据表(PDF) 13 Page - OKI electronic componets

部件名 ML2250
功能描述  2-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI
PDF  36 Pages
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制造商  OKI [OKI electronic componets]
网页  http://www.oki.com
标志 OKI - OKI electronic componets

ML2250 数据表(HTML) 13 Page - OKI electronic componets

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FEDL2250DIGEST-09
OKI Semiconductor
ML2250 family
13/36
QFP
Pin
WCSP pin
ML2256
WCSP pin
Symbol
Type
Description
24
F5
E6
D6/SCK
I/O
CPU interface data bus pin in the parallel input interface.
Usually outputs
“L” level when RD = “L” level.
Works as serial clock input pin in the serial input interface.
When the SCK input is at
“L” level on the falling edge of WR,
RD, DW
, the DI input is captured in the device on the rising
edge of SCK clock. And when the SCK input is at
“H” level
on the falling edge of WR, RD, DW, the DI input is captured
on the falling edge of SCK clock.
26
C4
D5
D7/DI
I/O
CPU interface data bus pin in the parallel input interface.
Usually output
“L” level when RD is at “L” level.
Works as serial data input pin in the serial input interface.
28
F3
E4
DAO
O
DAO pin outputs analog signal of 14-bit DAC.
29
E3
E3
AOUT
O
AOUT pin usually outputs the analog signal of 14-bit DAC
via voltage follower.
32
F1
D2
SERIAL
I
CPU interface switching pin.
Serial input interface at
“H” level. And parallel input interface
at
“L” level.
36
D2
D1
CS
I
CPU interface chip select pin.
When CS pin is at
“H” level, the WR, DW, and RD signals
cannot be input to the device.
37
E1
C2
OPTANA
I
Keep this pin
“L” level. The analog signal of 14-bit DAC is
output from DAO pin and from AOUT pin via voltage
follower.
42
C2
B2
WR
I
CPU interface write signal.
When CS pin is at
“H” level, the WR signal cannot be input to
the device.
2
B1
C3
DW
I
Data write signal when using EXT command for the voice
output.
Set the pin to
“H” level when not using EXT command.
When CS pin is at
“H” level, the DW signal cannot be input to
the device.
This pin has a pull-up resistor built in.
6
A3
A4
RD
I
CPU interface read signal.
When CS pin is at
“H” level, the RD signal cannot be input to
the device.
This pin has a pull-up resistor built in.
7, 8
B3, A4
B4
C4
TESTO1
TESTO2
O
Output pin for testing.
Keep this pin open.
30
F2
E2
AVDD
Analog power supply pin.
Insert a 0.1 F or larger bypass capacitor between this pin
and AGND pin.
13, 40
B5, C1
A6,B1
DVDD
Digital power supply pin.
Insert a 0.1 F or larger bypass capacitor between this pin
and DGND pin.
27
F4
E5
AGND
Analog ground pin.
17, 31,
39
C6, D1,
E2
C1,C7,E1
DGND
Digital ground pin.



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