ADP5074

Data Sheet

Rev. A | Page 10 of 17

THEORY OF OPERATION

SW

FB

INVERTER

PWM CONTROL

PVIN

ERROR AMP

EN

VREG

COMP

SLEW

SYNC/

FREQ

SS

GND

CURRENT

SENSE

START-UP

TIMERS

PLL

4µA

REF

CONTROL

OSCILLATOR

SLEW

L1

D1

THERMAL

SHUTDOWN

UVLO

OVP

VREF

VREG

FB

REFERENCE

GENERATOR

REF_1.6V

REF_1.6V

REF

POWER

GOOD

REF

PWRGD

VREG

(OPTIONAL)

HIGH VOLTAGE

BAND GAP

HIGH VOLTAGE

REGULATOR

AVIN

EN

Figure 21. Functional Block Diagram

PWM MODE

The inverting regulator in the ADP5074 operates at a fixed fre-

quency set by an internal oscillator. At the start of each oscillator

cycle, the MOSFET switch turns on, applying a positive voltage

until the current sense signal crosses the peak inductor current

threshold that turns off the MOSFET switch; this threshold is set

by the error amplifier output. During the MOSFET off time, the

inductor current declines through the external diode until the next

oscillator clock pulse starts a new cycle. The ADP5074 regulates the

output voltage by adjusting the peak inductor current threshold.

SKIP MODE

During light load operation, the regulator can skip pulses to

maintain output voltage regulation. Skipping pulses increases

the device efficiency. The COMP voltage is monitored internally

and when it falls below a threshold (due to the output voltage

rising above the target during a switching cycle), the next switching

cycle is skipped. This voltage is monitored on a cycle-by-cycle

basis. During skip operation, the output ripple is increased and

the ripple frequency varies. The choice of inductor defines the

output current below which skip mode occurs.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO circuitry monitors the AVIN pin voltage level. If the

regulator turns off. After the AVIN pin voltage rises above the

regulator is enabled.

OSCILLATOR AND SYNCHRONIZATION

A phase-locked loop (PLL)-based oscillator generates the internal

clock and offers a choice of two internally generated frequency

options or external clock synchronization. The switching frequency

is configured using the SYNC/FREQ pin options shown in Table 6.

For external synchronization, connect the SYNC/FREQ pin to a

suitable clock source. The PLL locks to an input clock within

Table 6. SYNC/FREQ Pin Options

SYNC/FREQ Pin

Switching Frequency

High

2.4 MHz

Low

1.2 MHz

External Clock

1× clock frequency

INTERNAL REGULATORS

The internal VREG regulator in the ADP5074 provides a stable

power supply for the internal circuitry. The VREG supply provides

a high signal for device configuration pins but must not be used

to supply external circuitry.

The VREF regulator provides a reference voltage for the inverting

regulator feedback network to ensure a positive feedback voltage

on the FB pin. A current-limit circuit is included for both internal

regulators to protect the circuit from accidental loading.