Data Sheet

ADP5303

Rev. B | Page 7 of 21

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A1

A2

A3

B1

B2

B3

C1

C2

C3

EN

PGND

PVIN

AGND

VINOK

SYNC/

MODE

VID

FB

SW

ADP5303

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

A1

SW

Switching Node Output for the Regulator.

A2

PVIN

Power Input for the Regulator.

A3

EN

Enable Input for the Regulator. Set this pin to logic low to disable the regulator.

B1

PGND

Power Ground.

B2

AGND

Analog Ground.

B3

SYNC/MODE

Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external

clock, connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz.

PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM

mode. When this pin is logic low, the regulator operates in hysteresis mode.

C1

VINOK

Output Power-Good Signal. This open-drain output is the power-good signal for the input voltage.

C2

FB

Feedback Sensing Input for the Regulator.

C3

VID

output voltage of the regulator (see Table 5).